A flexible lifecycle is managed thanks to multiple levels of readout protection and debug unlock with password. Besides these capabilities, the devices incorporate a secure firmware installation feature that allows the customer to secure the provisioning of the code during its production. ![]() It embeds the necessary security features to implement a secure boot, secure data storage and secure firmware update. The devices offer security foundation compliant with the TBSA (trusted-based security architecture) requirements from Arm ®. The devices embed high-speed memories (up to 2 Mbytes of flash memory and 786 Kbytes of SRAM), an FSMC (flexible external memory controller) for static memories (for devices with packages of 90 pins and more), two Octo-SPI flash memory interfaces (at least one Quad-SPI available on all packages) and an extensive range of enhanced I/Os and peripherals connected to three APB buses, three AHB buses and a 32-bit multi-AHB bus matrix. The Cortex ®-M33 core also implements a full set of DSP (digital signal processing) instructions and a MPU (memory protection unit) that enhances the application security. The Cortex ®-M33 core features a single-precision FPU (floating-point unit), that supports all the Arm ® single-precision data-processing instructions and all the data types. ![]() ![]() They operate at a frequency of up to 160 MHz. The STM32U575xx devices belong to an ultra-low-power microcontrollers family (STM32U5 series) based on the high-performance Arm ® Cortex ®-M33 32-bit RISC core.
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